Integrated circuits include metal connections that interconnect transistors and other circuit components of the integrated circuit. The metal connections are also used to provide the supply and ground reference voltages for the integrated circuit. The metal connections may be formed in multiple metal layers separated or isolated by dielectric layers. The multiple layers may be referred to as a metal stack. Metal connections in different layers may be interconnected to each other as desired using vertical interconnections or vias.
Integrated circuits may be subject to electrostatic discharge (ESD) events, which may involve a sudden flow of electricity between two electrically charged objects caused by contact, or an electrical short. When an ESD event occurs, an accumulation of charge from the sudden flow of electricity may generate an ESD voltage that may peak at a relatively high level, which may cause damage to electronic circuits. Integrated circuits may include ESD protection circuitry to protect against the harmful effects of ESD events. In order to do so, metal connections used for the ESD protection circuitry may be designed to discharge a sufficient amount of current generated from the ESD event in order to suppress the ESD voltage.
Reducing the production cost of a product in which an integrated circuit is implemented is often desirable. Two ways that the production cost may be reduced are reducing the area or size of the die on which the integrated circuit is formed and reducing the number of metal layers of the metal stack. However, reducing the number of metal layers may be undesirable from an ESD perspective because doing so reduces the number of metal layers available for use in discharging the current, thereby reducing the effectiveness of the ESD protection circuitry. Put another way, for a given integrated circuit configuration with a given number of metal layers, increasing the total number of metal layers of the metal stack in order to make available more metal layers for discharging ESD current may be cost prohibitive. As such, an integrated circuit configuration that increases the number of metal layers used in discharging ESD current without increasing the total number of metal layers in the metal stack may be desirable.